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GS8170LW72C-300 Datasheet(PDF) 5 Page - GSI Technology |
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GS8170LW72C-300 Datasheet(HTML) 5 Page - GSI Technology |
5 / 27 page GS8170LW36/72C-333/300/250/200 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.03 1/2005 5/27 © 2002, GSI Technology, Inc. Read Operations Pipelined Read Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins Single Data Rate (SDR) Pipelined Read. Write Operations Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low. Late Write In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT SRAMs SigmaRAM Late Write with Pipelined Read Read A Deselect Read B Read C Read D A B C D E Q(A) Q(B) Q(C) Q(D) CK Address ADV E1 W DQ CQ Read A Deselect Write B Read C Read D A B C D E Q(A) D(B) Q(C) Q(D) CK Address ADV E1 Bx W DQ CQ |
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