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M36P0R9070E0 Datasheet(PDF) 11 Page - STMicroelectronics |
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M36P0R9070E0 Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 26 page M36P0R9070E0 2 Signal descriptions 11/26 The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 8., Flash Memory DC Characteristics - Voltages). 2.11 PSRAM Chip Enable input (EP) The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep Power-down mode. 2.12 PSRAM Write Enable (WP) Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array. 2.13 PSRAM Output Enable (GP) Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. 2.14 PSRAM Upper Byte Enable (UBP) The Upper Byte En-able, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8- DQ15) to or from the upper part of the selected address during a Write or Read operation. 2.15 PSRAM Lower Byte Enable (LBP) The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0- DQ7) to or from the lower part of the selected address during a Write or Read operation. If both LBP and UBP are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as EP remains Low. 2.16 PSRAM Configuration Register Enable (CRP) When this signal is driven High, VIH, Write operations load either the value of the Refresh Configuration Register (RCR) or the Bus configuration register (BCR). |
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