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NM93C66LN Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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NM93C66LN Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 12 page Capacitance (Note 3) TA e 25 C f e 1 MHz Symbol Test Typ Max Units COUT Output Capacitance 5 pF CIN Input Capacitance 5 pF Note 1 Stress above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device This is a stress rating only and operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2 CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle (this is shown in the opcode diagrams in the following pages) Note 3 This parameter is periodically sampled and not 100% tested Note 4 Typical leakage values are in the 20 nA range Note 5 The shortest allowable SK clock period e 1fSK (as shown under the fSK parameter) Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet Within this SK period both tSKH and tSKL limits must be observed Therefore it is not allowable to set 1tSK e tSKH (minimum) a tSKL (minimum) for shorter SK cycle time operation AC Test Conditions VCC Range VIL VIH VIL VIH VOL VOH IOL IOH Input Levels Timing Levels Timing Levels 27V s VCC k 45V 03V18V 10V 08V15V g 10 mA (Extended Voltage Levels) 45V s VCC s 55V 04V24V 10V20V 04V24V b 21 mA04 mA (TTL Levels) Output Load 1 TTL Gate (CL e 100 pF) Functional Description The NM93C06LC46LC56LC66L device have 7 instruc- tions as described below Note that the MSB of any instruc- tion is a ‘‘1’’ and is viewed as a start bit in the interface sequence For the C06 and C46 the next 8 bits carry the op code and the 6-bit address for register selection For the C56 and C66 the next 10-bits carry the op code and the 8- bit address for register selection Read (READ) The READ instruction outputs serial data on the DO pin After a READ instruction is received the instruction and ad- dress are decoded followed by data transfer from the se- lected memory register into a 16-bit serial-out shift register A dummy bit (logical 0) precedes the 16-bit data output string Output data changes are initiated by a low to high transition of the SK clock EraseWrite Enable (WEN) When VCC is applied to the part it powers up in the Erase Write Disable (WDS) state Therefore all programming modes must be preceded by an EraseWrite Enable WEN instruction Once an EraseWrite Enable instruction is exe- cuted programming remains enabled until an EraseWrite Disable (WDS) instruction is executed or VCC is completely removed from the part Erase (ERASE) The ERASE instruction will program all bits in the selected register to the logical ‘‘1’’ state CS is brought low following the loading of the last address bit This falling edge of the CS pin initiates the self-timed programming cycle The DO pin indicates the READYBUSY status of the chip if CS is brought high after the tCS interval DO e logical ‘‘0’’ indicates that programming is still in progress DO e logical ‘‘1’’ indicates that the register at the address specified in the instruction has been erased and the part is ready for another instruction http www nationalcom 5 |
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