3

IDT77301

UtopiaFIFO™ 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO

Commercial and Industrial Temperature Ranges

Pin Description

Symbol

Name

I/O

Description

1-2, 4-8,

10, 100

DATA-b

O

Data bus output for FIFO-b. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with

BNE LOW: data bus outp ut is a data nibble (Q0-Q3); Q4-Q6 data lines unused; d ata out Q7 is an

output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and

hig h nibble transfer. Slave Mode with BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q7

lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.

11

SOCS-b

O

Start Of Cell (FIFO-b). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts

for all remaining byte transfers.

12

CLAVS-b

I

Cell Available (FIFO-b). CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.

13

I/O

Enable (FIFO-b). Master Mode:

place on the current clock cycle. Slave Mode:

data nibble (Q0-3) on the output bus on the next read clock edge.

14, 16-20,

22-24

DATA-c

O

Data bus output for FIFO-c. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with

BNE LOW: data bus outp ut is a data nibble (Q0-Q-3); Q4-Q6 data lines unused; d ata out Q7 is an

output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and

hig h nibble transfer. Slave Mode with BNE LOW: data bus output is a data nibble (Q1-Q3); Q4-Q7

lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.

25

SOCS-c

O

Start Of Cell (FIFO-c). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts

for all remaining byte transfers.

26

CLAVS-c

I

Cell Available (FIFO-c) CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.

28

I/O

Enable (FIFO-c). Master Mode:

place on the current clock cycle. Slave Mode:

data nibble (Q0-3) on the output bus on the next read clock edge.

29-32,

34-38

DATA-d

O

Data bus output for FIFO-d. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with

BNE LOW: data bus outp ut is a data nibble (Q0-Q3); Q4-Q6 data lines unused; d ata out Q7 is an

output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and

hig h nibble transfer. Slave Mode with BNE LOW; data bus output is a data nibble (Q0-Q3); Q4-Q7

lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.

40

SOCS-d

O

Start Of Cell (FIFO-d). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts

for all remaining byte transfers.

41

CLAVS-d

I

Cell Available (FIFO-d). CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.

42

I/O

Enable (FIFO-d). Master Mode:

place on the current clock cycle. Slave Mode:

data nibble (Q0-3) on the output bus on the next read clock edge.

43

ENR

I

Input port write enable. Each data write requires

44

CLAVR

O

Input port Cell space Available. Notifies the controlling agent the FIFO(s) selected by the address

bus can accept a complete cell.

46

SOCR

I

Input port Start of Cell. Assertion: first work is currently on bus.

47-53

Data 17-11/

P_CS 6-0

I

BSS low (18-Bit bus): Data bus input Data 11-Data 17

BSS high (9-bit bus): Input port for loading programmable registers.

3240 tbl 01