SN54LV165, SN74LV165

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SCES007B – MARCH 1995 – REVISED APRIL 1996

5

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

SN74LV165

VCC = 5.5 V

± 0.5 V

VCC = 3.3 V

± 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

0

50

0

40

0

30

MHz

t

Pulse duration

CLK high or low

14

18

22

ns

tw

Pulse duration

SH/LD low

14

18

22

ns

SH/LD high before CLK

↑

10

13

17

t

Setup time

SER before CLK

↑

8

11

14

ns

tsu

Setup time

CLK INH before CLK

↑

10

12

15

ns

Data before SH/LD

↑

8

12

17

th

Hold time

SER data after CLK

↑

6

6

5

ns

th

Hold time

Parallel data after SH/LD

↑

6

6

5

ns

(unless otherwise noted) (see Figure 1)

FROM

TO

SN54LV165

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5.5 V ± 0.5 V

VCC = 3.3 V ± 0.3 V

VCC = 2.7 V

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

MAX

fmax

50

90

40

75

30

MHz

CLK

20

24

20

38

47

tpd

SH/LD

QH or QH

19

24

19

36

44

ns

H

15

20

15

29

36

(unless otherwise noted) (see Figure 1)

FROM

TO

SN74LV165

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5.5 V ± 0.5 V

VCC = 3.3 V ± 0.3 V

VCC = 2.7 V

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

MAX

fmax

50

90

40

75

30

MHz

CLK

20

24

20

38

47

tpd

SH/LD

QH or QH

19

24

19

36

44

ns

H

15

20

15

29

36

PARAMETER

TEST CONDITIONS

VCC

TYP

UNIT

Cpd

Power dissipation capacitance

CL =50 pF

f=10MHz

3.3 V

33

pF

Cpd

Power dissi ation ca acitance

CL = 50 F,

f = 10 MHz

5 V

57

F

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.