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SN74LS221 Datasheet(PDF) 3 Page - ON Semiconductor

Part No. SN74LS221
Description  LOW POWER SCHOTTKY
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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SN74LS221
http://onsemi.com
3
OPERATIONAL NOTES
Once in the pulse trigger mode, the output pulse width is
determined by tW = RextCextIn2, as long as Rext and Cext are
within their minimum and maximum valves and the duty
cycle is less than 50%. This pulse width is essentially
independent of VCC and temperature variations. Output
pulse widths varies typically no more than
±0.5% from
device to device.
If the duty cycle, defined as being 100
@
tW
T
where T is the
period of the input pulse, rises above 50%, the output pulse
width will become shorter. If the duty cycle varies between
low and high valves, this causes the output pulse width to
vary in length, or jitter. To reduce jitter to a minimum, Rext
should be as large as possible. (Jitter is independent of Cext).
With Rext = 100K, jitter is not appreciable until the duty
cycle approaches 90%.
Although the LS221 is pin-for-pin compatible with the
LS123, it should be remembered that they are not
functionally identical. The LS123 is retriggerable so that the
output is dependent upon the input transitions once it is high.
This is not the case for the LS221. Also note that it is
recommended to externally ground the LS123 Cext pin.
However, this cannot be done on the LS221.
The SN74LS221 is a dual, monolithic, non-retriggerable,
high-stability one shot. The output pulse width, tW can be
varied over 9 decades of timing by proper selection of the
external timing components, Rext and Cext.
Pulse triggering occurs at a voltage level and is, therefore,
independent of the input slew rate. Although all three inputs
have this Schmitt-trigger effect, only the B input should be
used for very long transition triggers (
≥1.0 µV/s). High
immunity to VCC noise (typically 1.5 V) is achieved by
internal
latching
circuitry.
However,
standard
VCC
bypassing is strongly recommended.
The LS221 has four basic modes of operation.
Clear Mode:
If the clear input is held low, irregardless of
the previous output state and other input
states, the Q output is low.
Inhib-
it Mode:
If either the A input is high or the B input is
low, once the Q output goes low, it cannot
be retriggered by other inputs.
Pulse Trigger
Mode:
A transition of the A or B inputs as indicated
in the functional truth table will trigger the Q
output to go high for a duration determined
by the tW equation described above; Q will
go low for a corresponding length of time.
The Clear input may also be used to trigger
an output pulse, but special logic precondi-
tioning on the A or B inputs must be done
as follows:
Following any output triggering action
using the A or B inputs, the A input must
be set high OR the B input must be set
low to allow Clear to be used as a trigger.
Inputs should then be set up per the truth
table (without triggering the output) to
allow Clear to be used a trigger for the
output pulse.
If the Clear pin is routinely being used to
trigger the output pulse, the A or B inputs
must be toggled as described above
before and between each Clear trigger
event.
Once triggered, as long as the output
remains high, all input transitions (except
overriding Clear) are ignored.
Overriding
Clear Mode:
If the Q output is high, it may be forced low
by bringing the clear input low.




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