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74LS175 Datasheet(PDF) 2 Page - ON Semiconductor |
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74LS175 Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 8 page SN74LS175 http://onsemi.com 2 CONNECTION DIAGRAM DIP (TOP VIEW) Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input True Outputs Complemented Outputs D0 – D3 CP MR Q0 – Q3 Q0 – Q3 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. HIGH LOW (Note a) LOADING PIN NAMES LOGIC DIAGRAM NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. VCC = PIN 16 GND = PIN 8 = PIN NUMBERS LOGIC SYMBOL VCC = PIN 16 GND = PIN 8 12 1 2 36 7 11 14 15 10 45 13 9CP D0 D1 D2 D3 MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 DQ CP CD Q CP D3 D2 D1 D0 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 DQ CP CD Q MR 14 1 2 67 3 4 5 9 11 12 10 13 15 DQ CP CD Q DQ CP CD Q 14 13 12 11 10 9 1234 5 6 7 16 15 8 VCC MR Q3 Q3 D3 D2 Q2 Q2 CP Q0 Q0 D0 D1 Q1 Q1 GND |
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