5-6

FAST AND LS TTL DATA

SN54/74LS90

• SN54/74LS92 • SN54/74LS93

Sb l

P

Limits

Ui

Sb l

P

LS90

LS92

LS93

Ui

Symbol

Parameter

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

fMAX

CP0 Input Clock Frequency

32

32

32

MHz

fMAX

CP1 Input Clock Frequency

16

16

16

MHz

tPLH

tPHL

Propagation Delay,

CP0 Input to Q0 Output

10

12

16

18

10

12

16

18

10

12

16

18

ns

tPLH

tPHL

CP0 Input to Q3 Output

32

34

48

50

32

34

48

50

46

46

70

70

ns

tPLH

tPHL

CP1 Input to Q1 Output

10

14

16

21

10

14

16

21

10

14

16

21

ns

tPLH

tPHL

CP1 Input to Q2 Output

21

23

32

35

10

14

16

21

21

23

32

35

ns

tPLH

tPHL

CP1 Input to Q3 Output

21

23

32

35

21

23

32

35

34

34

51

51

ns

tPLH

MS Input to Q0 and Q3 Outputs

20

30

ns

tPHL

MS Input to Q1 and Q2 Outputs

26

40

ns

tPHL

MR Input to Any Output

26

40

26

40

26

40

ns

Sb l

P

Limits

Ui

Sb l

P

LS90

LS92

LS93

Ui

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Unit

tW

CP0 Pulse Width

15

15

15

ns

tW

CP1 Pulse Width

30

30

30

ns

tW

MS Pulse Width

15

ns

tW

MR Pulse Width

15

15

15

ns

trec

Recovery Time MR to CP

25

25

25

ns

RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize

and transfer HIGH data to the Q outputs

AC WAVEFORMS

Figure 1

Figure 2

Figure 3

*CP

Q

1.3 V

tPHL

tW

1.3 V

1.3 V

1.3 V

1.3 V

tPLH

*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.

MR & MS

CP

Q

MS

Q0 • Q3

(LS90)

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

tPHL

tW

tPLH

trec

tW

CP

trec