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ADD8608A8A-75BA Datasheet(PDF) 3 Page - A-Data Technology |
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ADD8608A8A-75BA Datasheet(HTML) 3 Page - A-Data Technology |
3 / 9 page A-Data ADD8608A8A Pin Description PIN NAME FUNCTION CK, /CK System Clock Differential clock input. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS Chip Select Disables or Enables device operation by masking or enabling all input except CK, CKE and DQ A0~A12 Address Row / Column address are multiplexed on the same pins. Row address : A0~A12 Column address : A0~A9 BS0~BS1 Banks Select Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. DQ0~DQ7 Data Data inputs / outputs are multiplexed on the same pins. /RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low /CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low /WE Write Enable Enables write operation and row recharge. VDD/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic. VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers. VREF Reference Voltage Reference voltage for inputs for SSTL interface. NC No Connection This pin is recommended to be left No Connection on the device. Block Diagram CK CKE Clock Generator Address /CS /RAS /CAS /WE DQM Mode Register Address Buffer & Refresh Counter Column Address Buffer & Refresh Counter Bank0 Bank2 Bank3 Bank1 Amplifier Column Decoder Data Control Circuit DQ0~DQ7 DQS Rev 2 April, 2002 3 |
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