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HD6412340TE Datasheet(PDF) 11 Page - Hitachi Semiconductor |
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HD6412340TE Datasheet(HTML) 11 Page - Hitachi Semiconductor |
11 / 907 page v Section 7 Data Transfer Controller .............................................................................. 173 7.1 Overview............................................................................................................................ 173 7.1.1 Features ................................................................................................................ 173 7.1.2 Block Diagram...................................................................................................... 174 7.1.3 Register Configuration ......................................................................................... 175 7.2 Register Descriptions......................................................................................................... 176 7.2.1 DTC Mode Register A (MRA)............................................................................. 176 7.2.2 DTC Mode Register B (MRB) ............................................................................. 178 7.2.3 DTC Source Address Register (SAR) .................................................................. 179 7.2.4 DTC Destination Address Register (DAR) .......................................................... 179 7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 179 7.2.6 DTC Transfer Count Register B (CRB) ............................................................... 180 7.2.7 DTC Enable Registers (DTCER) ......................................................................... 180 7.2.8 DTC Vector Register (DTVECR) ........................................................................ 181 7.2.9 Module Stop Control Register (MSTPCR) .......................................................... 182 7.3 Operation ........................................................................................................................... 183 7.3.1 Overview .............................................................................................................. 183 7.3.2 Activation Sources................................................................................................ 185 7.3.3 DTC Vector Table ................................................................................................ 186 7.3.4 Location of Register Information in Address Space ............................................ 189 7.3.5 Normal Mode........................................................................................................ 190 7.3.6 Repeat Mode ........................................................................................................ 191 7.3.7 Block Transfer Mode............................................................................................ 192 7.3.8 Chain Transfer...................................................................................................... 194 7.3.9 Operation Timing ................................................................................................. 195 7.3.10 Number of DTC Execution States........................................................................ 196 7.3.11 Procedures for Using DTC ................................................................................... 198 7.3.12 Examples of Use of the DTC................................................................................ 199 7.4 Interrupts............................................................................................................................ 201 7.5 Usage Notes ....................................................................................................................... 201 Section 8 I/O Ports ............................................................................................................ 203 8.1 Overview............................................................................................................................ 203 8.2 Port 1.................................................................................................................................. 208 8.2.1 Overview .............................................................................................................. 208 8.2.2 Register Configuration ......................................................................................... 209 8.2.3 Pin Functions........................................................................................................ 210 8.3 Port 2.................................................................................................................................. 219 8.3.1 Overview .............................................................................................................. 219 8.3.2 Register Configuration ......................................................................................... 219 8.3.3 Pin Functions........................................................................................................ 221 8.4 Port 3.................................................................................................................................. 230 8.4.1 Overview .............................................................................................................. 230 |
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