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SN54LS168J Datasheet(PDF) 6 Page - ON Semiconductor |
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SN54LS168J Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 6 page 5-6 FAST AND LS TTL DATA SN54/74LS168 • SN54/74LS169 AC WAVEFORMS Figure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Width Figure 2. Count Enable Trickle Input To Terminal Count Output Delays Figure 3. Clock to Terminal Delays Figure 4. Setup Time (ts) and Hold (th) for Parallel Data Inputs 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V CP Q OR TC tPHL tPLH tPLH tPHL CET TC 1/fmax tW 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V ts(H) ts(L) th(L) = 0 th(H) = 0 Q0 • Q1 • Q2 • Q3 CP TC tPLH tPHL 1.3 V 1.3 V 1.3 V 1.3 V P0 • P1 • P2 • P3 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V SR OR PE CP U/D TC ts(L) ts(H) th(L) = 0 th(H) = 0 ts(H) th(H) = 0 th(L) = 0 ts(H) ts(L) tPLH tPHL 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V ts(L) th(L) = 0 th(H) = 0 Figure 5. Setup Time and Hold Time for Count Enable and Parallel Enable Inputs, and Up-Down Control Inputs Figure 6. Up-Down Input to Terminal Count Output Delays The shaded areas indicate when the input is permitted to change for predictable output performance. CP CEP CET CP |
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