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MUN5214DW1T1 Datasheet(PDF) 1 Page - ON Semiconductor |
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MUN5214DW1T1 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 10 page © Semiconductor Components Industries, LLC, 2003 December, 2003 − Rev. 5 1 Publication Order Number: MUN5211DW1T1/D MUN5211DW1T1 Series Preferred Devices Dual Bias Resistor Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminates these individual components by integrating them into a single device. In the MUN5211DW1T1 series, two BRT devices are housed in the SOT−363 package which is ideal for low power surface mount applications where board space is at a premium. • Simplifies Circuit Design • Reduces Board Space • Reduces Component Count • Available in 8 mm, 7 inch/3000 Unit Tape and Reel MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1 and Q2) Rating Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current IC 100 mAdc THERMAL CHARACTERISTICS Characteristic (One Junction Heated) Symbol Max Unit Total Device Dissipation TA = 25°C Derate above 25 °C PD 187 (Note 1.) 256 (Note 2.) 1.5 (Note 1.) 2.0 (Note 2.) mW mW/ °C Thermal Resistance − Junction-to-Ambient RθJA 670 (Note 1.) 490 (Note 2.) °C/W Characteristic (Both Junctions Heated) Symbol Max Unit Total Device Dissipation TA = 25°C Derate above 25 °C PD 250 (Note 1.) 385 (Note 2.) 2.0 (Note 1.) 3.0 (Note 2.) mW mW/ °C Thermal Resistance − Junction-to-Ambient RθJA 493 (Note 1.) 325 (Note 2.) °C/W Thermal Resistance − Junction-to-Lead RθJL 188 (Note 1.) 208 (Note 2.) °C/W Junction and Storage Temperature TJ, Tstg − 55 to +150 °C 1. FR−4 @ Minimum Pad 2. FR−4 @ 1.0 x 1.0 inch Pad Preferred devices are recommended choices for future use and best overall value. DEVICE MARKING INFORMATION See specific marking information in the device marking table on page 2 of this data sheet. Q1 R1 R2 R2 R1 Q2 (1) (2) (3) (4) (5) (6) http://onsemi.com SOT−363 CASE 419B STYLE 1 MARKING DIAGRAM 1 6 XXd XX = Specific Device Code d = Date Code = (See Page 2) 1 6 |
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