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K4N51163QC-ZC Datasheet(PDF) 11 Page - Samsung semiconductor |
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K4N51163QC-ZC Datasheet(HTML) 11 Page - Samsung semiconductor |
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11 / 64 page  - 11 - Rev 1.5 Oct. 2005 512M gDDR2 SDRAM K4N51163QC-ZC (Refer to notes for informations related to this table at the bottom) Parameter Symbol - 25 - 2A - 33 - 36 Units Notes min max min max min max min max DQ output access time from CK/CK tAC -400 +400 -450 +450 -470 +470 -500 +500 ps DQS output access time from CK/CK tDQSCK -350 +350 -400 +400 -420 +420 -450 +450 ps CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK half period tHP min(tCL, tCH) x min (tCL, tCH) x min (tCL, tCH) x min (tCL, tCH) x ps 20,21 Clock cycle time, CL= x tCK 2500 8000 2.86 8.0 3.3 8.0 3.6 8.0 ns 24 DQ and DM input hold time tDH 125 x 175 x 195 x 225 x ps 15,16, 17 DQ and DM input setup time tDS 50 x 50 x 70 x 100 x ps 15,16, 17 Control & Address input pulse width for each input tIPW 0.6 x 0.6x0.6x0.6 x tCK DQ and DM input pulse width for each input tDIPW 0.35 x 0.35 x 0.35 x 0.35 x tCK Data-out high-impedance time from CK/ CK tHZ x tAC max x tAC max x tAC max x tAC max ps DQS low-impedance time from CK/CK tLZ (DQS) tAC min tAC max tAC min tAC max tAC min tAC max tAC min tAC max ps 27 DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max 2*tAC min tAC max 2* tAC min tAC max ps 27 DQS-DQ skew for DQS and associated DQ signals tDQSQ x200 x 310 x 320 x 340 ps 22 DQ hold skew factor tQHS x 300 x 410 x 420 x 440 ps 21 DQ/DQS output hold time from DQS tQH tHP - tQHS x tHP - tQHS x tHP - tQHS x tHP - tQHS x ps Write command to first DQS latching transition tDQSS -0.25 0.25 WL -0.25 WL +0.25 WL -0.25 WL +0.25 WL -0.25 WL +0.25 tCK DQS input high pulse width tDQSH 0.35 x 0.35 x 0.35 x 0.35 x tCK DQS input low pulse width tDQSL 0.35 x 0.35 x 0.35 x 0.35 x tCK DQS falling edge to CK setup time tDSS 0.2 x 0.2 x 0.2 x 0.2 x tCK DQS falling edge hold time from CK tDSH 0.2 x 0.2 x 0.2 x 0.2 x tCK Mode register set command cycle time tMRD 2 x 2 x 2 x 2 x tCK Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 19 Write preamble tWPRE 0.35 x 0.35 x 0.35 x 0.35 x tCK Address and control input hold time tIH 250 x 325 x 345 x375 x ps 14,16, 18 Address and control input setup time tIS 175 x 200 x 220 x250 x ps 14,16, 18 Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK 28 Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 28 Active to active command period for 1KB page size products tRRD 7.5 x 7.5 x 7.5 x7.5 x ns 12 Active to active command period for 2KB page size products tRRD 10 x 10 x 10 x10 x ns 12 9.3 Timing Parameters by Speed Grade |
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