PRELIMINARY
CY7C1338G
Document #: 38-05521 Rev. *A
Page 3 of 17
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Synchronous
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed
the 2-bit counter.
BWA,BWB
BWC,BWD
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
CE2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is
loaded.
CE3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is
loaded.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Pin Configurations (continued)
2
34
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
NC
DQC
DQD
DQC
DQD
AA
A
A
ADSP
VDDQ
CE2
A
DQC
VDDQ
DQC
VDDQ
VDDQ
VDDQ
DQD
DQD
NC
NC
VDDQ
VDD
CLK
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
AA
A
A
NC
A
A
A
A
A
A
A0
A1
DQA
DQC
DQA
DQA
DQA
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQA
DQA
DQA
DQA
DQB
VDD
DQC
DQC
DQC
VDD
DQD
DQD
DQD
DQD
ADSC
NC
CE1
OE
ADV
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
MODE
NC
NC
BWB
BWC
NC
VDD
NC
BWA
NC
BWE
BWD
ZZ
119-Ball BGA
A
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