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CY7C1338G-133BGXC Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C1338G-133BGXC
Description  4-Mbit (128K x 32) Flow-Through Sync SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1338G-133BGXC Datasheet(HTML) 8 Page - Cypress Semiconductor

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PRELIMINARY
CY7C1338G
Document #: 38-05521 Rev. *A
Page 8 of 17
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to VDDQ + 0.5V
DC Input Voltage ....................................–0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Ambient
Temperature]
VDD
VDDQ
Commercial
0°C to +70°C
3.3V
−5%/+10% 2.5V –5%
to VDD
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range [8, 9]
Parameter
Description
Test Conditions
CY7C1338G
Unit
Min.
Max.
VDD
Power Supply Voltage
3.135
3.6
V
VDDQ
I/O Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
V
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
2.0
V
VOL
Output LOW Voltage
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
0.4
V
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
0.4
V
VIH
Input HIGH Voltage
VDDQ = 3.3V
2.0
VDD + 0.3V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VIL
Input LOW Voltage[8]
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
IX
Input Load Current (except ZZ and
MODE)
GND
≤ V
I ≤ VDDQ
−55
µA
Input Current of MODE
Input = VSS
–30
µA
Input = VDD
5
µA
Input Current of ZZ
Input = VSS
–5
µA
Input = VDD
30
µA
IOZ
Output Leakage Current
GND
≤ V
I ≤ VDD, Output Disabled
–5
5
µA
IOS
Output Short Circuit Current
VDD = Max., VOUT = GND
–300
µA
IDD
VDD Operating Supply Current
VDD = Max., IOUT = 0 mA,
f = fMAX= 1/tCYC
7.5-ns cycle, 133 MHz
225
mA
8.0-ns cycle, 117 MHz
220
mA
10-ns cycle, 100 MHz
205
mA
ISB1
Automatic CE Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
7.5-ns cycle, 133 MHz
90
mA
8.0-ns cycle, 117 MHz
85
mA
10-ns cycle, 100 MHz
80
mA
ISB2
Automatic CE Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
All speeds
40
mA
ISB3
Automatic CE Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN≥VDDQ – 0.3V or VIN ≤ 0.3V,
f = fMAX, inputs switching
7.5-ns cycle, 133 MHz
75
mA
8.0-ns cycle, 117 MHz
70
mA
10-ns cycle, 100 MHz
65
mA
ISB4
Automatic CE Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
All speeds
45
mA
Shaded areas contain advance information.
Notes:
8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).
9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.


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