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25LC080AP Datasheet(PDF) 11 Page - Microchip Technology

Part # 25LC080AP
Description  8K SPI Bus Serial EEPROM
Download  24 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

25LC080AP Datasheet(HTML) 11 Page - Microchip Technology

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 2003 Microchip Technology Inc.
DS21808B-page 11
25XX080A/B
2.6
Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the Status
Register as shown in Table 2-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the Status Register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is also a
nonvolatile bit that is available as an enable bit for the WP
pin. The Write-Protect (WP) pin and the Write-Protect
Enable (WPEN) bit in the Status Register control the
programmable hardware write-protect feature. Hardware
write protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes to
nonvolatile bits in the Status Register are disabled. See
Table 2-4 for a matrix of functionality on the WPEN bit.
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3:
ARRAY PROTECTION
FIGURE 2-7:
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
BP1
BP0
Array Addresses
Write-Protected
00
none
01
upper 1/4
(0300h - 03FFh)
10
upper 1/2
(0200h - 03FFh)
11
all
(0000h - 03FFh)
SO
SI
CS
9
1011
12131415
01
0
0
0
0
00
765
4
21
0
instruction
data to Status Register
high-impedance
SCK
0
234567
1
8
3


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