© 2002 QuickLogic Corporation
www.quicklogic.com
1
•
•
•
•
•
•
• • • • • •
Device Highlights
High Performance & High Density
•
9,000 Usable PLD Gates with 82 I/Os
•
300 MHz 16-bit Counters, 400 MHz
Datapaths, 160+ MHz FIFOs
•
0.35
µm four-layer metal non-volatile
CMOS process for smallest die sizes
High Speed Embedded SRAM
•
8 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks
•
5 ns access times, each port independently
accessible
•
Fast and efficient for FIFO, RAM, and ROM
functions
Easy to Use / Fast Development
Cycles
•
100% routable with 100% utilization and
complete pin-out stability
•
Variable-grain logic cells provide high
performance and 100% utilization
•
Comprehensive design tools include high
quality Verilog/VHDL synthesis
Advanced I/O Capabilities
•
Interfaces with both 3.3 V and 5.0 V devices
•
PCI compliant with 3.3 V and 5.0 V busses
for -1/-2/-3/-4 speed grades
•
Full JTAG boundary scan
•
I/O Cells with individually controlled
Registered Input Path and Output Enables
Figure 1: QuickRAM Block Diagram
8
RAM
Blocks
160
High Speed
Logic Cells
Interface
QL4009 QuickRAM Data Sheet
9,000 Usable PLD Gate QuickRAM ESP Combining Performance,
Density and Embedded RAM
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
