QL4009-2PF100C datasheet(4/18 Pages) ETC1

Part #	QL4009-2PF100C

Description	9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM

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QL4009 QuickRAM Data Sheet Rev B

AC Characteristics at V

CC = 3.3 V, TA = 25° C (K = 1.00)

To calculate delays, multiply the appropriate K factor from Table 10: Operating Range by the

following numbers in the tables provided.

Figure 3: QuickRAM Logic Cell

Table 1: Logic Cell

Symbol

Parameter

Propagation Delays (ns)

Fanout (5)

1

2

3

4

5

t

PD

Combinatorial Delaya

a. These limits are derived from a representative selection of the slowest paths through the Quick-

RAM logic cell including typical net delays. Worst case delay values for specific paths should be

determined from timing analysis of your particular design.

1.4

1.7

1.9

2.2

3.2

tSU

Setup Timea

1.7

t

H

Hold Time

0.0

t

CLK

Clock to Q Delay

0.7

1.0

1.2

1.5

2.5

tCWHI

Clock High Time

1.2

t

CWLO

Clock Low Time

1.2

t

SET

Set Delay

1.0

1.3

1.5

1.8

2.8

tRESET

Reset Delay

0.8

1.1

1.3

1.6

2.6

t

SW

Set Width

1.9

t

RW

Reset Width

1.8

QS

A1

A2

A3

A4

A5

A6

F1

F2

F3

F4

F5

F6

QS

OP

B1

B2

C1

C2

MP

MS

D1

D2

E1

E2

NP

NS

QC

QR

OZ

AZ

QZ

NZ

FZ

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