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MT90820APR Datasheet(PDF) 5 Page - Zarlink Semiconductor Inc |
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MT90820APR Datasheet(HTML) 5 Page - Zarlink Semiconductor Inc |
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5 / 37 page  MT90820 Data Sheet 5 Zarlink Semiconductor Inc. 39 12 RESET Device Reset (Schmitt Trigger Input): This input (active LOW) puts the MT90820 in its reset state that clears the device internal counters, registers and brings STo0 - 15 and microport data outputs to a high impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held low for a minimum of 100 nsec to reset the device. 40 13 WFPS Wide Frame Pulse Select (Input): When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in ST-BUS/GCI mode. 41 - 48 14-21 A0 - A7 Address 0 - 7 (Input): When non-multiplexed CPU bus operation is selected, these lines provide the A0 - A7 address lines to the internal memories. 49 22 DS/RD Data Strobe / Read (Input): For multiplexed bus operation, this input is DS. This active high DS input works in conjunction with CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This active low input works in conjunction with CS to enable the read and write operations. For multiplexed bus operation, this input is RD. This active low input sets the data bus lines (AD0-AD7, D8-D15) as outputs. 50 23 R/W / WR Read/Write / Write (Input): In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls the direction of the data bus lines (AD0 - AD7, D8-D15) during a microprocessor access. For multiplexed bus operation, this input is WR. This active low input is used with RD to control the data bus (AD0 - 7) lines as inputs. 51 24 CS Chip Select (Input): Active low input used by a microprocessor to activate the microprocessor port of MT90820. 52 25 AS/ALE Address Strobe or Latch Enable (Input): This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed bus operation, connect this pin to ground. This pin is pulled low by an internal pull-down when not driven. 53 26 IM CPU Interface Mode (input): When IM is high, the microprocessor port is in the multiplexed mode. When IM is low, the microprocessor port is in non-multiplexed mode. This pin is pulled low by an internal pull-down when not driven. 55 - 62 32-39 AD0 - 7 Address/Data Bus 0 to 7 (Bidirectional): These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins are also the input address bits of the microprocessor port. 65 - 72 42-49 D8 - 15 Data Bus 8-15 (Bidirectional): These pins are the eight most significant data bits of the microprocessor port. 73 50 DTA Data Transfer Acknowledgement (Active Low Output): Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then tri-states, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is tri-stated. 74 55 CSTo Control Output (Output). This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1024 or 2048 bits per frame respectively. The level of each bit is determined by the CSTo bit in the connection memory. See External Drive Control Section. Pin Description Pin # Name Description 84 PLCC 100 MQFP |
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