IDT70V9099L6PF datasheet(4/17 Pages) IDT

Part #	IDT70V9099L6PF

Description	HIGH-SPEED 3.3V 128K x9/x8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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4 / 17 page

6.42

IDT70V9199/099L

High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

4

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

4. I/O0 - I/O7 for IDT70V9099.

Truth Table I—Read/Write and Enable Control(1,2,3)

Pin Names

Left Port

Right Port

Names

CE0L,

CE1L

CE0R,

CE1R

Chip Enables

R/WL

R/WR

Read/Write Enable

OEL

OER

Output Enable

A0L - A16L

A0R - A16R

Address

I/O0L - I/O8L(1)

I/O0R - I/O8R(1)

Data Input/Output

CLKL

CLKR

Clock

ADSL

ADSR

Address Strobe Enable

CNTENL

CNTENR

Counter Enable

CNTRSTL

CNTRSTR

Counter Reset

FT

/PIPEL

FT

/PIPER

Flow-Through / Pipeline

VDD

Power (3.3V)

VSS

Ground (0V)

4859 tbl 01

OE

CLK

CE0

CE1

R/W

I/O0-8(4)

MODE

X

↑

H

X

High-Z

Deselected–Power Down

X

↑

X

L

X

High-Z

Deselected–Power Down

X

↑

LH

L

DATAIN

Write

L

↑

LH

H

DATAOUT

Read

H

X

L

H

X

High-Z

Outputs Disabled

4859 tbl 02

Truth Table II—Address Counter Control(1,2)

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. CE0 and OE = VIL; CE1 and R/W = VIH.

3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.

4. ADS and CNTRST are independent of all other signals including CE0 and CE1.

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.

NOTE:

1. I/O0X - I/O7X for IDT70V9099.

External

Address

Internal

Address

Used

CLK

ADS

CNTEN

CNTRST

I/O(3)

MODE

XX

0

↑

XX

L(4)

DI/O(0)

Counter Reset to Address 0

An

X

An

↑

L(4)

XH

DI/O(n)

External Address Loaded into Counter

An

Ap

↑

HH

H

DI/O(p)

External Address Blocked—Counter disabled (Ap reused)

XAp

Ap + 1

↑

H

L(5)

HDI/O(p+1)

Counter Enabled—Internal Address generation

4859 tbl 03

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