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K6R1004C1C-P12 Datasheet(PDF) 5 Page - Samsung semiconductor |
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K6R1004C1C-P12 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 9 page PRELIMINARY Revision 3.0 - 5 - September 2001 PRELIMINARY K6R1004C1C-C/C-L, K6R1004C1C-I/C-P CMOS SRAM Address Data Out Previous Valid Data Valid Data TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tAA tRC tOH TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) CS Address OE Data out tAA tOLZ tLZ(4,5) tOH tOHZ tRC tOE tCO tPU tPD tHZ(3,4,5) 50% 50% VCC Current ICC ISB Valid Data WRITE CYCLE* * The above parameters are also guaranteed at industrial temperature range. Parameter Symbol K6R1004C1C-10 K6R1004C1C-12 K6R1004C1C-15 Unit Min Max Min Max Min Max Write Cycle Time tWC 10 - 12 - 15 - ns Chip Select to End of Write tCW 7 - 8 - 9 - ns Address Set-up Time tAS 0 - 0 - 0 - ns Address Valid to End of Write tAW 7 - 8 - 9 - ns Write Pulse Width(OE High) tWP 7 - 8 - 9 - ns Write Pulse Width(OE Low) tWP1 10 - 12 - 15 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output High-Z tWHZ 0 5 0 6 0 7 ns Data to Write Time Overlap tDW 5 - 6 - 7 - ns Data Hold from Write Time tDH 0 - 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - 3 - ns |
Similar Part No. - K6R1004C1C-P12 |
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Similar Description - K6R1004C1C-P12 |
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