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P1819AG-08SR Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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P1819AG-08SR Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
2 / 9 page November 2005 P1819 rev 1.7 Note Book LCD Panel EMI Reduction IC 2 of 9 Notice: The information in this document is subject to change without notice. VDD VDD Pin Configuration Pin Description Pin# 1819A/B/C/D 1819E/F/G/H/Q Pin Name Type Description 1 1 XIN / CLKIN I Crystal Connection or external frequency input.This pin has dual functions. It can be connected to either an external crystal or an external reference clock 2 2 VSS P Ground Connection. Connect to system ground. 3 SRS I Spread range select. Digital logic input used to select frequency deviation (Refer Spread Deviation Selection Table). This pin has an internal pull-up resistor. 3 D_C / NC I Digital logic input used to select Down (LOW) or Center (HIGH) spread options (Refer Spread Deviation Selection Table). This pin has an internal pull-up resistor. 4 4 ModOUT O Spread spectrum clock output. (Refer Input Frequency and Modulation Rate Table and Spread Deviation Selection Table) 5 5 REF O Non-modulated Reference clock output of the input frequency. 6 6 PD# I Power down control pin. Pull LOW to enable Power- Down mode. This pin has an internal pull-up resistor. 7 7 VDD P Power Supply for the entire chip. 8 8 XOUT O Crystal Connection. Input connection for an external crystal. If using an external reference, this pin must be left unconnected. Note: Pin 3 is NC in P1819Q PD# XOUT REF 1 2 3 4 5 6 7 8 P1819 A/B/C/D XIN/ CLKIN VSS SRS ModOUT REF 1 2 3 4 5 6 7 8 P1819 E/F/G/H/Q XIN / CLKIN VSS D_C / NC ModOUT PD# XOUT |
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