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ASM706 Datasheet(PDF) 3 Page - Alliance Semiconductor Corporation |
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ASM706 Datasheet(HTML) 3 Page - Alliance Semiconductor Corporation |
3 / 16 page ASM706 P/ R/ S/ T/ J 3 of 16 Notice: The information in this document is subject to change without notice 3/3.3/4.0 V µP Supervisor Circuits ASM708 R/ S/ T/ J October 2003 rev 1.0 Pin Description Pin Number Name Function ASM706P ASM706R/S/T/J ASM708R/S/T/J DIP/ SO MicroSO DIP/ SO MicroSO DIP/ SO MicroSO 1 313 13 MR Manual reset input. The active LOW input triggers a reset pulse. It is pulled HIGH by a 20k Ω pull-up resistor. It is compatible with TTL/CMOS signals when VCC = 5V. It can be shorted to ground through a mechanical switch. Leave folating or connect to VCC if the function is not used. 2 424 24 VCC Monitored power supply input. 3 535 35 GND Ground. 4 646 46 PFI Power-fail input voltage monitor. With PFI less than 1.25V, PFO goes LOW. Connect PFI to Ground when not in use. 5 757 57 PFO Power-fail output. The output is active LOW and sinks current when PFI is less than 1.25V. If not used, leave the pin unconnected. 6 868 - - WDI Watchdog input. WDI controls the internal watch- dog timer. A HIGH or LOW signal for 1.6sec at WDI allows the internal timer to run-out, setting WDO low. A rising or falling edge must occur at WDI within 1.6 seconds or WDO goes LOW. The watchdog function is disabled by floating WDI. The internal watchdog timer clears when: RESET is asserted; WDI is three-stated ; or WDI sees a ris- ing or falling edge. - - - - 6 8 NC Not Connected - - 7 1 7 1 RESET Active LOW reset output. Pulses LOW for 200ms when triggered, and stays LOW whenever VCC is below the reset threshold. RESET remains LOW for 200ms after VCC rises above the reset thresh- old or MR goes from HIGH to LOW. A watchdog timeout will not trigger RESET unless WDO is con- nected to MR. |
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