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ASM5P23S04A-2-08-ST Datasheet(PDF) 3 Page - Alliance Semiconductor Corporation |
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ASM5P23S04A-2-08-ST Datasheet(HTML) 3 Page - Alliance Semiconductor Corporation |
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3 / 15 page  September 2005 ASM5P23S04A rev 1.3 3.3 Zero ‘SpreadTrak’ Delay Buffer 3 of 15 Notice: The information in this document is subject to change without notice. Zero Delay and Skew Control For applications requiring zero input-output delay, all outputs must be equally loaded. To close the feedback loop of ASM5P23S04A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. Pin Configuration Pin Description for ASM5P23S04A Pin # Pin Name Description 1 REF 1 Input reference frequency, 5V tolerant input 2 CLKA1 2 Buffered clock output, bank A 3 CLKA2 2 Buffered clock output, bank A 4 GND Ground 5 CLKB1 2 Buffered clock output, bank B 6 CLKB2 2 Buffered clock output, bank B 7 VDD 3.3V supply 8 FBK PLL feedback input Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. ASM5P23S04A 5 6 7 8FBK VDD CLKB2 CLKB1 4 3 2 1 GND CLKA1 REF CLKA2 |
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