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K7Q161854A-FC10 Datasheet(PDF) 2 Page - Samsung semiconductor |
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K7Q161854A-FC10 Datasheet(HTML) 2 Page - Samsung semiconductor |
2 / 17 page 512Kx36 & 1Mx18 QDRTM b4 SRAM - 2 - Rev 1.0 July. 2002 K7Q163654A K7Q161854A 72 512Kx36-bit, 1Mx18-bit QDRTM SRAM FEATURES FUNCTIONAL BLOCK DIAGRAM • 2.5V+0.1V/-0.1V Power Supply. • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O . • Separate independent read and write data ports with concurrent read and write operation. • HSTL I/O. • Full data coherency, providing most current data . • Synchronous pipeline read with self timed late write. • Registered address, control and data input/output. • DDR(Double Data Rate) Interface on read and write ports. • Fixed 4-bit burst for both read and write operation. • Clock-stop supports to reduce current. • Two input clocks(K and K) for accurate DDR timing at clock rising edges only. • Two input clocks for output data(C and C) to minimize clock-skew and flight-time mismatches. • Single address bus. • Byte writable function. • Sepatate read/write control pin(R and W) • Simple depth expansion with no data contention. • Programmable output impedance. • JTAG 1149.1 compatible test access port. • 165FBGA(11x15 ball aray FBGA) with body size of 13x15mm R ADDRESS W C C D(Data in) ADD REG DATA REG CLK GEN CTRL LOGIC 512Kx36 1Mx18 MEMORY ARRAY WRITE DRIVER K K BWX 36 (or 18) SELECT OUTPUT CONTROL Notes: 1. Numbers in ( ) are for x18 device. 72 17(or 18) 17 (or 18) 36 (or 18) Q(Data Out) QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology. 4 (or 2) 72(or 36) 72(or 36) 144 Organization Part Number Cycle Time Access Time Unit X36 K7Q163654A-FC20 5.0 2.2 ns K7Q163654A-FC16 6.0 2.5 ns K7Q163654A-FC13 7.5 3.0 ns K7Q163654A-FC10 10.0 3.0 ns X18 K7Q161854A-FC20 5.0 2.2 ns K7Q161854A-FC16 6.0 2.5 ns K7Q161854A-FC13 7.5 3.0 ns K7Q161854A-FC10 10.0 3.0 ns (or 36) (or 36) (or 72) |
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