July 2005

ASM5I961P

rev 0.2

Low Voltage Zero Delay Buffer

2 of 14

Notice: The information in this document is subject to change without notice.

Pin Configuration

Figure 2. ASM5I961P 32-Lead Package Pinout (Top View)

Table 1: Pin Configuration

Pin #

Pin Name

I/O

Type

Function

2,3

PCLK, PCLK

¯¯¯¯¯

Input

LVCMOS

PLL reference clock signal

7

FB_IN

Input

LVCMOS

PLL feedback signal input, connect to a QFB

output

4

F_RANGE

Input

LVCMOS

PLL frequency range select

6

OE

¯¯

Input

LVCMOS

Output enable/disable

31,30,29,27,26,25,23,22,21

,19,18,17,15,14,13,11,10

Q0 - Q16

Output

LVCMOS

Clock outputs

9

QFB

Output

LVCMOS

PLL feedback signal output, connect to a

FB_IN

1,12,20,28

GND

Supply

Power

Negative power supply

5

VCCA

Supply

Power

PLL positive power supply (analog power

supply).

The

ASM5I961P

requires

an

external RC filter for the analog power

supply pin VCCA. Please see applications

section for details.

8,16,24,32

VCC

Supply

Power

Positive power supply for I/O and core

25

26

27

28

29

30

31

32

24 23 22 21 20 19 18 17

1

2

3

4

5

6 7

8

16

15

14

13

12

11

10

9

Q4

Q3

GND

Q2

Q1

Q0

VCC

Q5

Q15

GND

Q14

Q13

Q12

VCC

Q16

QFB

ASM5I961C

ASM5I961P