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ASM3P623S00BF-08-TT Datasheet(PDF) 3 Page - Alliance Semiconductor Corporation |
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ASM3P623S00BF-08-TT Datasheet(HTML) 3 Page - Alliance Semiconductor Corporation |
3 / 16 page July 2005 ASM3P623S00A/B/C/D/E/F rev 1.0 Zero Cycle Slip Peak EMI Reduction IC 3 of 16 Notice: The information in this document is subject to change without notice. Pin Description for ASM3P623S00A/B/C Pin # Pin Name Description 1 CLKIN 2 Input reference frequency, 5V-tolerant input 2 NC No Connect 3 SS% 4 Spread Spectrum Selection 4 GND Ground 5 SSON 4 Spread Spectrum enable and disable option When SSON is HIGH, the spread spectrum is enabled and when LOW, it turns off the spread spectrum. 6 CLKOUT 1,3 Buffered clock output 7 VDD 3.3V supply 8 NC No Connect Pin Description for ASM3P623S00D/E/F Pin # Pin Name Description 1 CLKIN 2 Input reference frequency, 5V tolerant input 2 CLKOUT1 3 Buffered clock output 3 VDD 3.3V supply 4 SS% 4 Spread Spectrum Selection 5 GND Ground 6 CLKOUT2 3 Buffered clock output 7 CLKOUT3 3 Buffered clock output 8 DLY CNTRL The pin is used to skew the outputs such that they align with the input. The skew can is in the range of 100-200pS 9 SSON 4 Spread Spectrum enable and disable option. When SSON is HIGH, the spread spectrum is enabled and when LOW, it turns off the spread spectrum. 10 CLKOUT4 3 Buffered clock output 11 CLKOUT5 3 Buffered clock output 12 GND Ground 13 VDD 3.3V supply 14 CLKOUT6 3 Buffered clock output 15 CLKOUT7 3 Buffered clock output 16 CLKOUT8 3 Buffered clock output Notes: 1. This output is driven and has an internal feedback for the PLL. 2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-up on these inputs. |
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Similar Description - ASM3P623S00BF-08-TT |
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