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AS29F200T-70SC Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS29F200T-70SC Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 20 page  3UHOLPLQDU\#LQIRUPDWLRQ 3UHOLPLQDU\#LQIRUPDWLRQ 3UHOLPLQDU\#LQIRUPDWLRQ 3UHOLPLQDU\#LQIRUPDWLRQ Copyright ©1998 Alliance Semiconductor. All rights reserved. ® $65<)533 $65<)533 $65<)533 $65<)533 ','#4407333<0$1#72:233 ','#4407333<0$1#72:233 ','#4407333<0$1#72:233 ','#4407333<0$1#72:233 $//,$1&(#6(0,&21'8&725 $//,$1&(#6(0,&21'8&725 $//,$1&(#6(0,&21'8&725 $//,$1&(#6(0,&21'8&725 4444 89#589.ð;245;.ð49#&026#)ODVK#((3520 89#589.ð;245;.ð49#&026#)ODVK#((3520 89#589.ð;245;.ð49#&026#)ODVK#((3520 89#589.ð;245;.ð49#&026#)ODVK#((3520 )HDWXUHV • Organization: 256K×8 or 128K×16 • Sector architecture - One 16K; two 8K; one 32K; and three 64K byte sectors - Boot code sector architecture—T (top) or B (bottom) - Erase any combination of sectors or full chip • Single 5.0±0.5V power supply for read/write operations • Sector protection • High speed 55/70/90/120 ns address access time • Automated on-chip programming algorithm - Automatically programs/verifies data at specified ad- dress • Automated on-chip erase algorith - Automatically preprograms/erases chip or specified sec- tors • 10,000 write/erase cycle endurance • Hardware RESET pin - Resets internal state machine to read mode • Low power consumption - 20 mA typical read current - 30 mA typical program current - 300 µA typical standby current - 1 µA typical standby current (RESET = 0) • JEDEC standard software, packages and pinouts -48-pin TSOP -44-pin SO • Detection of program/erase cycle completion -DQ7 DATA polling - DQ6 toggle bit - RY/BY output • Erase suspend/resume - Supports reading data from a sector not being erased • Low VCC write lock-out below 2.8V /RJLF#EORFN#GLDJUDP X decoder VCC VSS Cell matrix Y decoder Y gating Data latch Chip enable Input/output buffers Sector protect Command register Program/erase control VCC detector Erase voltage generator Program voltage generator Timer A0–A16 CE OE STB STB Output enable Logic RY/BY WE BYTE RESET DQ0–DQ15 switches A-1 3LQ#DUUDQJHPHQW 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A14 A15 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC A6 A5 A4 A3 A2 A1 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 44-pin SO 21 22 DQ3 DQ11 A10 A11 A12 A13 2 RY/BY 3 NC 4 A7 1 NC 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 WE A8 A9 RESET 48-pin TSOP AS29F200 6HOHFWLRQ#JXLGH 29F200-55 29F200-70 29F200-90 29F200-120 Unit Maximum access time tAA 55 70 90 120 ns Maximum chip enable access time tCE 55 70 90 120 ns Maximum output enable access time tOE 25 30 35 50 ns |
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