AS7C33256PFD18B

®

1/31/05; v.1.2

Alliance Semiconductor

P. 4 of 19

Functional description

The AS7C33256PFD18B is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) devices

organized as 262,144 words × 18 bits and incorporate a pipeline for highest frequency on any given technology.

frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the

controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent

internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip

address register. When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE.

In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are

carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock

edge that samples ADSP asserted but is sampled on all subsequent clock edges. Address is incremented internally for the next

access of the burst when ADV is sampled LOW and both address strobes are HIGH. Burst mode is selectable with the LBO

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable

GWE writes all 18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more

bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s).

BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are

disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled

LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW. This device operates in

double-cycle deselect feature during read cycles.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC

and ADSP are as follows:

• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).

• Master chip select CE0 blocks ADSP, but not ADSC.

The AS7C33256PFD18B operates from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.

These devices are available in a 100-pin 14×20 mm TQFP package.

TQFP capacitance

* Guaranteed not tested

TQFP thermal resistance

Parameter

Symbol

Test conditions

Min

Max

Unit

Input capacitance

-

5

pF

I/O capacitance

-

7

pF

Description

Conditions

Symbol

Typical

Units

Thermal resistance

1 This parameter is sampled

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

1–layer

40

°C/W

4–layer

22

°C/W

Thermal resistance

8

°C/W