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AS7C32096A-20TCN Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C32096A-20TCN Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
1 / 9 page February 2005 Preliminary Information Copyright © Alliance Semiconductor. All rights reserved. AS7C32096A 3.3V 256K × 8 CMOS SRAM ® 2/24/05, v. 1.0 Alliance Semiconductor P. 1 of 9 Features • Industrial and commercial temperature • Organization: 262,144 words × 8 bits • Center power and ground pins • High speed - 10/12/15/20 ns address access time - 4/5/6/7 ns output enable access time • Low power consumption: ACTIVE - 650 mW / max @ 10 ns • Low power consumption: STANDBY - 28.8 mW / max CMOS • Equal access and cycle times • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packages - 44-pin TSOP 2 • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Logic block diagram 262,144 × 8 Array (2,097,152) Input buffer I/O8 I/O1 OE CE WE Column decoder Control Circuit A0 A1 A2 A3 A4 A5 A6 A7 VCC GND A8 A9 Pin arrangement s GND VCC I/O6 I/O5 NC A13 A12 A11 A10 NC A4 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A5 A6 A7 A8 A9 I/O8 I/O7 A1 A2 A3 A0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 A15 A14 A16 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 3 4 1 NC NC NC NC NC NC NC NC NC OE A17 44-pin TSOP 2 Selection guide –10 –12 –15 –20 Unit Maximum address access time 10 12 15 20 ns Maximum output enable access time 4 5 6 7 ns Maximum operating current Industrial 180 160 140 110 mA Commercial 170 150 130 100 mA Maximum CMOS standby current 8 8 8 8 mA |
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