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AS7C25512PFD32A-166TQCN Datasheet(PDF) 10 Page - Alliance Semiconductor Corporation |
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AS7C25512PFD32A-166TQCN Datasheet(HTML) 10 Page - Alliance Semiconductor Corporation |
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10 / 19 page  ® AS7C25512PFD32A AS7C25512PFD36A 2/10/05, v. 1.2 Alliance Semiconductor 10 of 19 Timing characteristics over operating range Snooze Mode Electrical Characteristics Parameter Sym –166 –133 Unit Notes1 1 See “Notes” on page 16. Min Max Min Max Clock frequency fMax – 166 – 133 MHz Cycle time tCYC 6– 7.5 – ns Clock access time tCD –3.5 –3.8 ns Output enable low to data valid tOE –3.5 –3.8 ns Clock high to output low Z tLZC 0–0– ns 2,3,4 Data output invalid from clock high tOH 1.5 – 1.5 – ns 2 Output enable low to output low Z tLZOE 0–0– ns 2,3,4 Output enable high to output high Z tHZOE – 3.5 - 3.8 ns 2,3,4 Clock high to output high Z tHZC – 3.5 - 3.8 ns 2,3,4 Output enable high to invalid output tOHOE 0–0– ns Clock high pulse width tCH 2.4 – 2.4 – ns 5 Clock low pulse width tCL 2.3 – 2.4 – ns 5 Address setup to clock high tAS 1.5 – 1.5 – ns 6 Data setup to clock high tDS 1.5 – 1.5 – ns 6 Write setup to clock high tWS 1.5 – 1.5 – ns 6,7 Chip select setup to clock high tCSS 1.5 – 1.5 – ns 6,8 Address hold from clock high tAH 0.5 – 0.5 – ns 6 Data hold from clock high tDH 0.5 – 0.5 – ns 6 Write hold from clock high tWH 0.5 – 0.5 – ns 6,7 Chip select hold from clock high tCSH 0.5 – 0.5 – ns 6,8 ADV setup to clock high tADVS 1.5 – 1.5 – ns 6 ADSP setup to clock high tADSPS 1.5 – 1.5 – ns 6 ADSC setup to clock high tADSCS 1.5 – 1.5 – ns 6 ADV hold from clock high tADVH 0.5 – 0.5 – ns 6 ADSP hold from clock high tADSPH 0.5 – 0.5 – ns 6 ADSC hold from clock high tADSCH 0.5 – 0.5 – ns 6 Description Conditions Symbol Min Max Units Current during Snooze Mode ZZ > VIH ISB2 40 mA ZZ active to input ignored tPDS 2cycle ZZ inactive to input sampled tPUS 2cycle ZZ active to SNOOZE current tZZI 2cycle ZZ inactive to exit SNOOZE current tRZZI 0cycle |
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