Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

AS7C25512NTD36A-133TQC Datasheet(PDF) 4 Page - Alliance Semiconductor Corporation

Part # AS7C25512NTD36A-133TQC
Description  2.5V 512K x 32/36 Pipelined SRAM with NTD
Download  18 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C25512NTD36A-133TQC Datasheet(HTML) 4 Page - Alliance Semiconductor Corporation

  AS7C25512NTD36A-133TQC Datasheet HTML 1Page - Alliance Semiconductor Corporation AS7C25512NTD36A-133TQC Datasheet HTML 2Page - Alliance Semiconductor Corporation AS7C25512NTD36A-133TQC Datasheet HTML 3Page - Alliance Semiconductor Corporation AS7C25512NTD36A-133TQC Datasheet HTML 4Page - Alliance Semiconductor Corporation AS7C25512NTD36A-133TQC Datasheet HTML 5Page - Alliance Semiconductor Corporation AS7C25512NTD36A-133TQC Datasheet HTML 6Page - Alliance Semiconductor Corporation AS7C25512NTD36A-133TQC Datasheet HTML 7Page - Alliance Semiconductor Corporation AS7C25512NTD36A-133TQC Datasheet HTML 8Page - Alliance Semiconductor Corporation AS7C25512NTD36A-133TQC Datasheet HTML 9Page - Alliance Semiconductor Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 18 page
background image
®
AS7C25512NTD32A/36A
12/23/04, v 2.2
Alliance Semiconductor
P. 4 of 18
Functional Description
The AS7C25512NTD32A/36A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory
(SRAM) organized as 524,288 words × 32 or 36 bits and incorporates a LATE LATE Write.
This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD) architecture, featuring an enhanced
write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce
overall bandwidth for applications requiring random access or read-modify-write operations.
NTDdevices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or
one-cycle flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read
pipeline to clear. With NTD, write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full
32/36 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is
applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled
for write operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-
selected by any of the three chip enable inputs. In pipelined mode, a two cycle deselect latency allows pending read or write
operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C25512NTD32A/36A operates with a 2.5V ± 5% power supply for the device core (VDD). These devices are
available in a 100-pin TQFP package.
TQFP capacitance
* Guaranteed not tested
TQFP thermal resistance
Parameter
Symbol
Test conditions
Min
Max
Unit
Input capacitance
CIN*
VIN = 0V
-
5
pF
I/O capacitance
CI/O*
VOUT = 0V
-
7
pF
Description
Conditions
Symbol
Typical
Units
Thermal resistance
(junction to ambient)1
1 This parameter is sampled
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer
θJA
40
°C/W
4–layer
θJA
22
°C/W
Thermal resistance
(junction to top of case)1
θJC
8
°C/W


Similar Part No. - AS7C25512NTD36A-133TQC

ManufacturerPart #DatasheetDescription
logo
Alliance Semiconductor ...
AS7C25512NTF32A ALSC-AS7C25512NTF32A Datasheet
423Kb / 18P
   2.5V 512K x 32/36 Flowthrough Synchronous SRAM with NTD
AS7C25512NTF32A-10TQC ALSC-AS7C25512NTF32A-10TQC Datasheet
423Kb / 18P
   2.5V 512K x 32/36 Flowthrough Synchronous SRAM with NTD
AS7C25512NTF32A-10TQCN ALSC-AS7C25512NTF32A-10TQCN Datasheet
423Kb / 18P
   2.5V 512K x 32/36 Flowthrough Synchronous SRAM with NTD
AS7C25512NTF32A-10TQI ALSC-AS7C25512NTF32A-10TQI Datasheet
423Kb / 18P
   2.5V 512K x 32/36 Flowthrough Synchronous SRAM with NTD
AS7C25512NTF32A-10TQIN ALSC-AS7C25512NTF32A-10TQIN Datasheet
423Kb / 18P
   2.5V 512K x 32/36 Flowthrough Synchronous SRAM with NTD
More results

Similar Description - AS7C25512NTD36A-133TQC

ManufacturerPart #DatasheetDescription
logo
Alliance Semiconductor ...
AS7C33512NTD32A ALSC-AS7C33512NTD32A Datasheet
425Kb / 18P
   3.3V 512K x 32/36 Pipelined SRAM with NTD
AS7C251MNTD32A ALSC-AS7C251MNTD32A Datasheet
436Kb / 18P
   2.5V 1M x 32/36 Pipelined SRAM with NTD
AS7C25512NTF32A ALSC-AS7C25512NTF32A Datasheet
423Kb / 18P
   2.5V 512K x 32/36 Flowthrough Synchronous SRAM with NTD
AS7C25512PFS32A ALSC-AS7C25512PFS32A Datasheet
522Kb / 19P
   2.5V 512K x 32/36 pipelined burst synchronous SRAM
AS7C25512PFD32A ALSC-AS7C25512PFD32A Datasheet
523Kb / 19P
   2.5V 512K x 32/36 pipelined burst synchronous SRAM
AS7C331MNTD32A ALSC-AS7C331MNTD32A Datasheet
441Kb / 18P
   3.3V 1M x 32/36 Pipelined SRAM with NTD
AS7C3364NTD32B ALSC-AS7C3364NTD32B Datasheet
437Kb / 19P
   3.3V 64K x 32/36 Pipelined SRAM with NTD
AS7C251MNTF32A ALSC-AS7C251MNTF32A Datasheet
414Kb / 18P
   2.5V 1M x 32/36 Flowthrough SRAM with NTD
AS7C33512NTF32A ALSC-AS7C33512NTF32A Datasheet
425Kb / 18P
   3.3V 512K x 32/36 Flowthrough Synchronous SRAM with NTD
AS7C252MNTD18A ALSC-AS7C252MNTD18A Datasheet
436Kb / 18P
   2.5V 2M x 18 Pipelined SRAM with NTD
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com