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AS7C4096A-10JI Datasheet(PDF) 4 Page - Alliance Semiconductor Corporation |
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AS7C4096A-10JI Datasheet(HTML) 4 Page - Alliance Semiconductor Corporation |
4 / 10 page ® AS7C4096A 5/27/05, v. 1.1 Alliance Semiconductor P. 4 of 10 Key to switching waveforms Read waveform 1 (address controlled)2,5,6,8 Read waveform 2 (CE, OE controlled)2,5,7,8 Read cycle (over the operating range)2,8 Parameter Symbol –10 –12 –15 –20 Unit Notes Min Max Min Max Min Max Min Max Read cycle time tRC 10 –12– 15 – 20 – ns Address access time tAA –10 – 12 – 15–20 ns 2 Chip enable (CE) access time tACE –10 – 12 – 15–20 ns 2 Output enable (OE) access time tOE –5– 6–6–6 ns Output hold from address change tOH 3–3 –3–3– ns 4 CE Low to output in low Z tCLZ 3–3 –3–3– ns 3,4 CE High to output in high Z tCHZ –5– 6–7–9 ns 3,4 OE Low to output in low Z tOLZ 0–0 –0–0– ns 3,4 OE High to output in high Z tOHZ –5– 6–7–9 ns 3,4 Power up time tPU 0–0 –0–0– ns 3,4 Power down time tPD –10 – 12 – 15–20 ns 3,4 Undefined/don’t care Falling input Rising input Address DOUT Data valid tOH tAA tRC current Supply OE DOUT tOE tOLZ tACE tCHZ tCLZ tPU tPD ICC ISB 50% 50% tOHZ Data valid tRC1 CE |
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