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9240LPRPQE Datasheet(PDF) 2 Page - Maxwell Technologies |
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9240LPRPQE Datasheet(HTML) 2 Page - Maxwell Technologies |
2 / 18 page 2 01.10.05 REV 6 All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP TABLE 1. 9240LP PIN DESCRIPTION PIN NUMBER NAME DESCRIPTION 1 DVSS Digital Ground 2, 29 AVSS Analog Ground 3 DVDD 5V Digital Supply 4, 28 AVDD 5V Analog Supply 5 NC No Connect 6 DRVDD Digital Output Driver Supply 7 CLK Clock Input Pin 8 LPTSTATUS A 0 to 5V square-wave is output during the deci- sion time and protect time. Normally low. 9 LPTBIT The LPT circuit will crowbar the power supplies to the 9240 for as long as a logic high is applied. Used to verify operation of the LPT. Normally a logical low or ground is applied to this input. 10 NC No Connect 11 BIT 14 Least Significant Data Bit (LSB) 12-23 BIT 13-BIT 2 Data Output Bits 24 BIT 1 Most Significant Data Bits (MSB) 25 OTR Out of Range 26, 27, 30 NC No Connect 31 SENSE Reference Select 32 VREF Reference I/O 33 REFCOM Reference Common 34, 38 NC No Connect 35 BIAS 1 1. See Speed/Power programmability section. Power/Speed Programming 36 CAPB Noise Reduction Pin 37 CAPT Noise Reduction Pin 39 CML Common-Mod Level (Midsupply) 40 LPTVREF Protected Reference I/O 41 VINA Analog Input Pin (+) 42 VINB Analog Input Pin (-) 43 LPTDVDD Protected 5V Digital Supply 44 LPTAVDD Protected 5V Analog Supply |
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