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9240LP Datasheet(PDF) 7 Page - Maxwell Technologies |
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9240LP Datasheet(HTML) 7 Page - Maxwell Technologies |
7 / 18 page 7 01.10.05 REV 6 All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC 9240LP LOGIC OUTPUTS (with DRVDD = 5V) High Level Output Voltage (I OH = 50 µ A) High Level Output Voltage (I OH = 0.5 mA) Low Level Output Voltage (I OL = 1.6 mA) Low Level Output Voltage (I OL = 50 µ A) Output Capacitance 1, 2, 3 V OH V OH V OL V OL C OUT 5 4.5 2.4 0.4 0.1 -- V min V min V max V max pF typ 1. Due to the voltage drop across the LPT circuiry the CLOCK signal must be no greater than AVDD - 0.5V 2. Guaranteed by design TABLE 6. 9240LP SWITCHING CHARACTERISTICS1 (T A = -55 TO +125° C WITH AVDD = 5V, DVDD = 5V, DRVDD = 5V, RBIAS = 2 KW, CL = 20 PF) 1. Guaranteed by design PARAMETER SYMBOL MIN TYP MAX UNITS Clock Period CLOCK Pulse width High CLOCK Pulse width Low Output Delay Pipeline Delay (Latency) t C t CH t CL t OD 100 45 45 8 -- -- -- -- 13 -- -- -- -- 19 --3 ns ns ns ns Clock Cycles TABLE 5. 9240LP DIGITAL SPECIFICATIONS (AVDD = 5V, DVDD = 5V, T A = -55 TO +125° C, UNLESS OTHERWISE SPECIFIED) PARAMETER SUBGROUPS SYMBOL MIN TYP MAX UNIT |
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