VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com
7
Program Memory Structure
Program Memory
The VRS550 includes 8k of on-chip Flash that can be
used as general program memory. The Flash memory
size of the VRS560 is 16k.
FIGURE 3: VRS560 / VRS550 INTERNAL PROGRAM MEMORY
VRS550
Flash Memory
(8k Bytes)
0000h
3FFFh
VRS560
Flash Memory
(16k Bytes)
0000h
1FFFh
Program Status Word Register
The register below contains the program state flags.
These flags may be read or written to by the user.
TABLE 6: PROGRAM STATUS WORD REGISTER (PSW) - SFR DOH
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
-
P
Bit
Mnemonic
Description
7
CY
Carry Bit
6
AC
Auxiliary Carry Bit from bit 3 to 4.
5
F0
User definer flag
4
RS1
R0-R7 Registers bank select bit 0
3
RS0
R0-R7 Registers bank select bit 1
2
OV
Overflow flag
1
-
-
0
P
Parity flag
RS1
RS0
Active Bank
Address
0
0
0
00h-07h
0
1
1
08h-0Fh
1
0
2
10h-17h
1
1
3
18-1Fh
Data Pointer
The VRS550 and VRS560 have one 16-bit data
pointer. The DPTR is accessed through two SFR
addresses: DPL located at address 82h and DPH
located at address 83h.
Data Memory
The VRS550 and the VRS560 have a total of: 256 bytes
of RAM configured like the internal memory structure of
a standard 8052.
FIGURE 4: VRS550 /VRS560 RAM MEMORY
Upper 128 bytes
(Can only be accessed in
indirect addressing mode)
Lower 128 bytes
(Can be accessed in indirect and
direct addressing mode)
SFR
(Can only be accessed in direct
addressing mode)
FF
80
Lower 128 bytes (00h to 7Fh, Bank 0 & Bank 1)
The lower 128 bytes of data memory (from 00h to 7Fh)
can be summarized in the following points:
• Address range 00h to 7Fh can be accessed in
direct and indirect addressing modes.
• Address range 00h to 1Fh includes R0-R7
registers area.
• Address range 20h to 2Fh is bit addressable.
• Address range 30h to 7Fh is not bit addressable
and can be used as general-purpose storage.
Upper 128 bytes (80h to FFh, Bank 2 & Bank 3)
The upper 128 bytes of the data memory ranging from
80h to FFh can be accessed using indirect addressing
or by using the bank mapping in direct addressing
mode.
FIGURE 5: VRS550 / VRS560 RAM STRUCTURE
Register s Bank 0
R7
-
R0
Register s Bank 1
R7
-
R0
Register s Bank 2
R7
-
R0
Register s Bank 3
R7
-
R0
80 Bytes of
General Purpose RAM
00h
08h
10h
18h
20h
07
06
05
04
03
02
01
00
0F
0 E
0D
0C
0B
0 A
09
08
77
76
75
74
73
72
71
70
7F
7 E
7D
7C
7B
7 A
79
78
30h
128 Bytes of
Indirect Access RAM
(SP, R0,R1)
80h
7Fh
FFh
2Fh
SFR Area
Direct or Bit Access
Only
FFh
85
84
83
82
81
80
P0
SP
DPL
DPH
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