VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com
8
Description of Peripherals
System Control Register
The register represented in the following table is used
for system control. The WDRESET bit (7) indicates if
the system has been reset due to the overflow of the
Watch Dog Timer.
The bit 0 of the SYSCON register is the ALE output
inhibit bit. Setting this bit to 1 will inhibit the Fosc/6
clock signal output to the ALE pin.
TABLE 7: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH
7
6
5
4
3
2
1
0
WDRESET
Unused
XRAME
ALEI
Bit
Mnemonic
Description
7
WDRESET
This is the Watch Dog Timer reset bit. It
will be set to 1 when the reset signal
generated by WDT overflows.
6
Unused
-
5
Unused
-
4
Unused
-
3
Unused
-
2
Unused
-
1
Unused
-
0
ALEI
ALE output inhibit bit, which is used to
reduce EMI.
Power Control Register
The VRS550 / VRS560 devices provide two power
saving modes: Idle and Power Down. These two
modes serve to reduce the power consumption of the
device.
In Idle mode, the processor is stopped but the oscillator
is still running. The content of the RAM, I/O state and
SFR registers are maintained. Timer operation is
maintained, as well as the external interrupts.
This mode is useful for applications in which stopping
the processor to save power is required. The processor
will be woken up when an external event, triggering an
interrupt, occurs.
In Power Down mode, the oscillator of the VRS550 /
VRS560 is stopped. This means that all the peripherals
are disabled. The content of the RAM and the SFR
registers, however, is maintained.
The minimum VCC in Power down Mode is 2V
These power saving modes are controlled by the
PDOWN and IDLE bits of the PCON register at
address 87h.
TABLE 8: POWER CONTROL REGISTER (PCON) - SFR 87H
7
6
5
4
3
2
1
0
Unused
RAM1
RAM0
Bit
Mnemonic
Description
7
SMOD
1: Double the baud rate of the serial port
frequency that was generated by Timer 1.
0: Normal serial port baud rate generated by
Timer 1.
6
5
4
3
GF1
General Purpose Flag
2
GF0
General Purpose Flag
1
PDOWN
Power down mode control bit
0
IDLE
Idle mode control bit
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