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ICS853031AYLF Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS853031AYLF Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 19 page 853031AY www.icst.com/products/hiperclocks.html REV. B SEPTEMBER 16, 2004 1 Integrated Circuit Systems, Inc. ICS853031 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION The ICS853031 is a low skew, high performance 1-to-9 Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS853031 has two selectable clock in- puts. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, LVDS, CML, or SSTL input levels. The clock enable is internally syn- chronized to eliminate runt pulses on the outputs during asyn- chronous assertion/deassertion of the clock enable pin. Guaranteed output skew and part-to-part skew characteristics make the ICS853031 ideal for high performance workstation and server applications. HiPerClockS™ ICS FEATURES • 9 differential 2.5V/3.3V LVPECL/ECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL, • PCLK, nPCLK supports the following input types: LVPECL, LVDS, CML, SSTL • Output frequency: 1.6GHz (typical) • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK or nPCLK inputs • Output skew: 20ps (typical) • Part-to-part skew: 75ps (typical) • Propagation delay: 875ps (typical) • LVPECL mode operating voltage supply range: V CC = 2.375V to 3.465V, VEE = 0V • ECL mode operating voltage supply range: V CC = 0V, VEE = -2.375V to -3.465V • -40°C to 85°C ambient operating temperature • Lead-Free package available • Pin compatible with ICS8531-01 BLOCK DIAGRAM PIN ASSIGNMENT 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 VCCO Q3 nQ3 Q4 nQ4 Q5 nQ5 VCCO ICS853031 VCC CLK nCLK CLK_SEL PCLK nPCLK VEE CLK_EN 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8 CLK nCLK PCLK nPCLK D Q LE CLK_EN CLK_SEL 0 1 |
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