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48SD1616 Datasheet(PDF) 8 Page - Maxwell Technologies |
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48SD1616 Datasheet(HTML) 8 Page - Maxwell Technologies |
8 / 42 page 48SD1616 8 All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 256Mb (4-Meg X 16-Bit X 4-Banks) SDRAM 01.07.05 REV 4 Command Operation Command Truth Table The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins: Note: H: V IH L: VIL x VIH or VIL V: Valid address input Ignore command (DESL): When this command is set (CS = High), the SDRAM ignores command input at the clock. However, the internal status is held. No Operation (NOP): This command is not an execution command. However, the internal operations continue. Column address strobe and read command (READ): This command starts a read operation. In addition, the start address of a burst read is determined by the column address (AY0 to AY8) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. COMMAND SYMBOL N -1 N CS RAS CAS WE BA0/ BA1 A10 A0 TO A12 Ignore command DESL H x H x x x x x x No Operation NOP H x L H H H x x x Column Address and Read command READ H x LH LH V L V Read with auto-pre- charge READ A H x L H L H V H V Column Address and write command WRIT H x L H L L V L V Write with auto-pre- charge WRIT A H x L H L L V H V Row address strobe and bank active ACTV H x L L H H V V V Precharge select bank PRE H x L L H L V L x Precharge all banks PALL H x L L H L x H x Refresh REF/SELF H LLLL H x x x Mode register set MRS H x LLLL V V V |
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