6

All data sheets are subject to change without notice

©2002 Maxwell Technologies

All rights reserved.

4 Megabit (512K x 8-Bit) SRAM

32C408B

05.02.02 Rev 7

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and

WE going low: A write ends at the earliest transition among CS going high or WE going high. t

of write to end of write.

3. t

4. t

5. t

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write

cycle.

8. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.

9. D

10.When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.