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A54SX32P-1BG208PP Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part # A54SX32P-1BG208PP
Description  54SX Family FPGAs
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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A54SX32P-1BG208PP Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers

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v3.1
5
54S X Fam ily F P G A s
The C-cell implements a range of combinatorial functions
up to 5-inputs (Figure 3). Inclusion of the DB input and its
associated inverter function dramatically increases the
number
of
combinatorial
functions
that
can
be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the SX
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to integrate
a 3-input exclusive-OR function into a single C-cell. This
facilitates construction of 9-bit parity-tree functions with 2
ns propagation delays. At the same time, the C-cell
structure is extremely synthesis friendly, simplifying the
overall design and reducing synthesis time.
Ch ip A r ch ite c ture
The SX family’s chip architecture provides a unique
approach to module organization and chip routing that
delivers the best register/logic mix for a wide variety of new
and emerging applications.
Mo dul e Organ i zati on
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance, Actel
has further organized these modules into SuperClusters
(Figure 4 on page 6). SuperCluster 1 is a two-wide grouping
of Type 1 clusters. SuperCluster 2 is a two-wide group
containing one Type 1 cluster and one Type 2 cluster. SX
devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
significantly more combinatorial logic than flip-flops.
Figure 2 • R-Cell
Figure 3 • C-Cell
Direct
Connect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS
CKP
CLRB
PSETB
Y
DQ
Routed
Data Input
S0
S1
D0
D1
D2
D3
DB
A0
B0
A1
B1
Sa
Sb
Y


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