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Si 30 00
8
Rev. 1.1
Figure 2. Serial Interface Timing Diagram
Table 7. Switching Characteristics—Serial Interface
(VA, VD = 5 V ±5% or 3.3 V ±10%, TA = 70°C for K-grade, CL = 20 pF)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Cycle Time, SCLK
tc
354
1/256 Fs
—
ns
SCLK Duty Cycle
tdty
—50
—
%
Delay Time, SCLK
↑ to FSYNC ↓
td1
—
—
10
ns
Delay Time, SCLK
↑ to SDO Valid
td2
—
—
20
ns
Delay Time, SCLK
↑ to FSYNC ↑
td3
—
—
10
ns
Setup Time, SDI, before SCLK
↓
tsu
25
—
—
ns
Hold Time, SDI, after SCLK
↓
th
20
—
—
ns
Setup Time, FSYNC (mode 2) before
MCLK
↓
tsu
25
—
—
ns
Hold Time, FSYNC (mode 2) after
MCLK
↓
th
20
—
—
ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V
SCLK
VOH
VOL
FSYNC
D15
D14
D1
D0
... D2
16-bit
D15
D14
D1
D0
... D2
SDO
16-bit
SDI
td1
td2
tsu
th
FSYNC
(mode 0)
(mode 1)
td3
td3
tc
High-Z
High-Z
FSYNC
(mode 2)
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