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TM497BBK32-70 Datasheet(PDF) 1 Page - Texas Instruments |
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TM497BBK32-70 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 9 page TM497BBK32, TM497BBK32S 4194304 BY 32-BIT DYNAMIC RAM MODULE SMMS433B – JANUARY 1993 – REVISED JUNE 1995 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 D Organization...4194304 × 32 D Single 5-V Power Supply (±10% Tolerance) D 72-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets D Utilizes Eight 16-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages D Long Refresh Period 32 ms (2048 Cycles) D All Inputs, Outputs, Clocks Fully TTL Compatible D 3-State Output D Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks D Enhanced Page Mode Operation With CAS-Before-RAS ( CBR ), RAS-Only, and Hidden Refresh D Presence Detect D Performance Ranges: ACCESS ACCESS ACCESS READ OR TIME TIME TIME WRITE tRAC tAA tCAC CYCLE (MAX) (MAX) (MAX) (MIN) ’497BBK32-60 60 ns 30 ns 15 ns 110 ns ’497BBK32-70 70 ns 35 ns 18 ns 130 ns ’497BBK32-80 80 ns 40 ns 20 ns 150 ns D Low Power Dissipation D Operating Free-Air-Temperature Range 0 °C to 70°C D Gold-Tabbed Version Available:† TM497BBK32 D Tin-Lead (Solder) Tabbed Version Available: TM497BBK32S description The TM497BBK32 is a 16M-byte dynamic random-access memory (DRAM) organized as four times 4 194 304 × 8 in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed of eight TMS417400DJ, 4 194 304 × 4-bit DRAMs, each in 24/26-lead plastic small-outline J-lead (SOJ) packages mounted on a substrate with decoupling capacitors. The TMS417400DJ is described in the TMS417400 data sheet. The TM497BBK32 SIMM is available in the single-sided BK leadless module for use with sockets. The TM497BBK32 SIMM features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation from 0 °C to 70°C. operation The TM497BBK32 operates as eight TMS417400DJs connected as shown in the functional block diagram and Table 1. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. refresh The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. power up To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh (RAS-only or CBR ) cycle. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright © 1995, Texas Instruments Incorporated |
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