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11-323
RF3000
Rev A4 031216
Notes:
1. AC tests performed with CL=20pF, IOL=2mA, and IOH=-1mA. Input reference level all inputs VCC/2. Test VIH=VCC,
VIL=0V; VOH=VOL=VCC/2.
2. Not tested, but characterized at initial design and at major process/design changes.
3. Measured from VIL to VIH.
4. TX PE must be inactive before going active to generate a new packet.
5. IOUT/QOUT are modulated after last chip of valid data to provide ramp-down time for RF/IF circuits.
6. A new search will begin after last bit of 802.11 packet in 802.11 modes.
7. Centered about 1.7V VREF.
8. Accurate to within ±3dB of final gain setting.
Parameter
Specification
Unit
Condition
Min.
Typ.
Max.
I/Q ADC
Full Scale Input Voltage
0.7
+10%
VP-P
See Note 7.
Input Bandwidth
11
MHz
Input Capacitance
5
pF
Input Impedance
50
k
Ω
I/Q DAC
Full Scale Output Voltage
200
mV
See Note 7.
Sample Rate
11
MHz
Resolution
6
bits
DNL
0.5
LSB
INL
0.5
1.0
LSB
Tested for monotonicity.
TX VGC DAC
Maximum Gain Output Voltage
1.2
V
Minimum Gain Output Voltage
2.0
V
Resolution
6
bits
DNL
0.5
LSB
INL
0.5
1.0
LSB
Tested for monotonicity.
RX VGC DAC
Maximum Gain Output Voltage
1.2
V
Minimum Gain Output Voltage
2.0
V
Resolution
6
bits
DNL
0.5
LSB
INL
0.5
1.0
LSB
Tested for monotonicity.
Control Port Timing
Characteristics
SPI Mode
Mode Switching Characteristics.
See Figure 3.
C CLK Clock Frequency
6
MHz
fCLK
CS High Time Between
Transmissions
1.1
µSt
CSH
CS Falling to C CLK Edge
22
nS
tCSS
C CLK Low Time
68
nS
tCLKL
C CLK High Time
68
nS
tCLKH
CD IN to C CLK Setup Time
42
nS
tDSU
C CLK Rising to Data Hold Time
16
nS
tDHLD
C CLK Falling to CD OUT Stable
47
nS
tPD
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