9

TH7834C

1997A–IMAGE–05/02

Note:

1. For ¼ of total CCD register.

Note:

The maximum clock frequency is limited by the dark signal increase. Full performance for 5 MHz.

Table 4. Drive Clock Capacitances Operating Frequencies(1)

Symbol

Function/Clock

Capacitive Network

Total

Max. Frequency

Φ

Register Main Transport Clock

Φ

Φ

for one CCD

(1)

10 MHz

Φ

Register End Transfer Clock

≤ 50 pF per phase

10 MHz

Φ

Transfer Clock

80 pF per phase

Pulse duration

≥ 2µs

Period:

≥ 608.6 µs

(4 outputs mode)

Φ

Antiblooming And Exposure

Time Control

100 pF per phase

Φ

Reset Clock

≤ 50 pF per phase

10 MHz

ΦL1

ΦL2

160pF

250pF

320pF

ΦP

ΦL2

15pF

VSS

VST

15pF

50pF

ΦA

15pF

VSS

VST

60pF

Table 5. Static and Dynamic Electrical Characteristics

Parameter

Symbol

Value

Unit

Remarks

Min.

Typ.

Max.

DC Output Level (Pins: 1, 28, 29, 56)

V

ref

10

V

Output Impedance (Pins: 1, 28, 29,

56)

Z

S

400

600

Ω

Maximum Data Output Frequency

Per Channel

5

10

MHz

(Note:)

Input Current On Active Pins 4, 6, 7,

8, 10, 11, 12, 13, 16, 17, 18, 19, 21,

23, 32, 34, 35, 36, 38, 39, 40, 41, 44,

45, 46, 47, 49, 51

<< 1

2

µA

V

with all other

pins = 0V

Amplifier Drain Supply Current (Per

I

10

16

mA

V

Static Power Dissipation (Per V

165

240

mW