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ATF1516AE-7 Datasheet(PDF) 5 Page - ATMEL Corporation |
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ATF1516AE-7 Datasheet(HTML) 5 Page - ATMEL Corporation |
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5 / 76 page  5 ATF15xxAE Family 2398E–12/01 Figure 2. ATF15xxAE Family Macrocell with Enhanced Features In Red Product Terms and Select Mux Within each macrocell are five product terms. Each product term may receive as its inputs any combination of the signals from the switch matrix or regional foldback bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the fitter software, which selects the optimum macrocell configuration. OR/XOR/ CASCADE Logic Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5- input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func- tions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimiza- tion of product terms. The XOR gate may be fed from the flip-flop output to emulate T- and JK- type flip-flops, or fed to the buried feedback to synthesize an extra latch. Foldback Bus Each macrocell can also generate a foldback product term. This signal goes to the regional bus and is available to the 16 macrocells in a given logic block. The foldback is an inverse polarity of one of the macrocell’s product terms. Although Cascade Logic is the preferred method for expanding the number of macrocell inputs to as many as 40, the 16 foldback terms in each region can also generate additional fan-in sum terms with nominal additional delay. REGIONAL FOLDBACK BUS 16 LOGIC FOLDBACK I/O Pin 3 GCK[0:2] GCLEAR CASOUT D/T*/L CE AR AP Q CASIN I/O Pin SLEW RATE OPEN COLLECTOR 6 GOE[0:5] Reduced Power Option 80 GLOBAL BUS 40 1 2 3 4 5 PT1 PT2 PT3 PT5 PT4 SWITCH MATRIX OUTPUTS * T flip-flop synthesised !Q Q !Q CK/CK/LE GOE SWITCH MATRIX GOE [0:5] |
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