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ATF1504AE-4 Datasheet(PDF) 9 Page - ATMEL Corporation |
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ATF1504AE-4 Datasheet(HTML) 9 Page - ATMEL Corporation |
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9 / 76 page  9 ATF15xxAE Family 2398E–12/01 latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. All pin transitions are ignored until the PD pin is brought low. When the power- down feature is enabled for PD1 or PD2, that pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals. The power-down option is selected in the design source file. Power Consumption Estimates An estimate of power consumption can be made based on typical designs and operation con- ditions, but because it is sensitive to these factors, power consumption must be verified with actual pattern and operation conditions. The equations given below are based on a pattern of 16-bit up/down counters in each logic block and may be used to estimate power consumption for both operating modes. Standby Power 1. P standby = Iccstandby x Vsupply Where: I ccstandby = the standby current given for the particular device and standby mode (e.g., pin con- trolled Power Down) V supply= the power supply voltage Active Power 2. P active = Pinternal + Pload = Iccinternal x Vsupply + Pload Where: I ccinternal = the internal current estimated from equation 3 below V supply= the power supply voltage P load = depends on the device output load capacitance and switching frequency on each out- put pin. P load and additional power savings at low frequencies using Atmel Input Transition Detection (“L” versions) can be estimated according to the methods discussed in the Atmel Application Note “Saving Power with Atmel PLDs” 3. I ccinternal = [K1 x (MCinuse – MCreducedpower )] + (K2 x MCreducedpower) + (K3 x MCinuse x fop x NS) Where: MC reducedpower = the number of macrocells operating at reduced power (from fitter report file) MC inuse= the number of macrocells in use (from fitter report file. Unused macrocells are pow- ered down.) NS = the proportion of logic nodes switching (typically 10-20%) f op = the switching frequency K 1, K2,and K3 = device constants given in the table below. Note: Shaded data is preliminary and subject to change without notice. Device K1 K2 K3 ATF1502AE 0.6 0.3 0.015 ATF1504AE 0.6 0.3 0.015 ATF1508AE 0.6 0.3 0.015 ATF1516AE 0.6 0.3 0.015 ATF1532AE 0.6 0.3 0.015 |
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