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BCRTM-5
**
Pin internally pulled up.
+
Pin at high impedance when not asserted
++
Bidirectional pin.
*
Formerly MEMWIN.
++
++
+
+
+
*
*
*
*
*
*
LCC, flatpack pin number not in parentheses.
() Pingrid array pin identification in parentheses.
TAZ
TAO
RAZ
RAO
TBZ
TBO
RBZ
RBO
RTA0
RTA1
RTA2
RTA3
RTA4
RTPTY
CLK
MCLK
MCLKD2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
13 (K3)
14 (L2)
17
18
(L4)
(K6)
15
16
19
20
(L3)
(K5)
(L5)
(K4)
28 (K8) **
29 (L9) **
30 (L10) **
31 (K9) **
32 (L11) **
68 (A6)
69 (A4)
70 (B4)
25 (K7)
26 (J7)
27 (L8)
72 (A2)
75 (B2)
33 (K10) **
73 (B3)*
56 (A10)
57 (A9)
67 (B5)
58 (B8)
61 (B7)
60 (C7)
53 (A11)
52 (C10)
59 (A8)
54 (B10)
62 (A7)
55 (B9)
66 (A5)
11
(A3)
74
(K2)
12
(A1)
10 (J2)
24 (L7)
34
(J10)
35
(K11)
36
37
38
39
40
41
44
45
46
47
48
49
50
51
(J11)
(H10)
(H11)
(G9)
(G10)
(G11)
(E9)
(E11)
(E10)
(F11)
(D11)
(D10)
(C11)
(B11)
9
8
7
6
5
4
3
2
83
82
81
80
79
78
77
76
(K1)
(J1)
(H2)
(H1)
(G3)
(G2)
(G1)
(F1)
(E1)
(E2)
(F2)
(D1)
(D2)
(C1)
(B1)
(C2)
23
43
64
84
1
22
42
63
(L6)
(F9)
(C6)
(E3)
(F3)
(J6)
(F10)
(B6)
21
65
(J5)
(C5)
71
(L1)
BIPHASE OUT
BIPHASE IN
TERMINAL
ADDRESS
STATUS
SIGNALS
DMA
SIGNALS
CONTROL
SIGNALS
ADDRESS
LINES
DATA
LINES
POWER
GROUND
CLOCK
SIGNALS
+
++
++
++
2.0 PIN IDENTIFICATION AND DESCRIPTION
+
*
*
STDINTL
STDINTP
HPINT
TIMERON
COMSTR
SSYSF
BCRTF
CHA/B
TEST
DMAR
DMAG
DMAGO
DMACK
BURST
TSCTL
RD
WR
CS
AEN
BCRTSEL
LOCK
MRST
EXTOVR
RRD
RWR
MEMCSI
MEMCSO
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
Figure 2. BCRT Functional Pin Description
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