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STANDARD SERIAL COMMUNICATION (HDQ) TIMING

BREAK

7 bit

ADDRESS

1 bit

R/W

8 bit

DATA

(a) Break and Break Recovery Timing;

(b) Host Transmitted Bit Timing;

(c) bq26150 Transmitted Bit Timing;

(d) bq26150 to Host Response Timing

bq26150

SLUS641A – JANUARY 2005 – REVISED JULY 2005

over recommended operating temperature and supply voltage range (unless otherwise noted) See Figure 1

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power up delay

Power capacitor charge time

100

ms

Break timing

190

µs

Break recovery

40

µs

Host bit window

190

µs

Host sends 1

0.5

50

µs

Host sends 0

86

145

µs

bq26150 to host response

190

320

µs

bq26150 bit window

190

250

µs

bq26150 sends 1

32

50

µs

bq26150 sends 0

80

145

µs

Figure 1. HDQ Bit Timing Diagrams

3