3-36

HFA-0003, HFA-0003L

Applications Information

HFA-0003L Latch Functionality

The Latch Enable (LE) pin of the HFA-0003L controls the

function of the on chip latch. When the LE input is at an ECL

Logic 1, the latch is open (transparent) and the comparator

functions normally. When the LE input switches to a Logic 0,

the outputs are latched in unambiguous states dependant on

the current input state, providing the set-up and hold times

are met. If the latch function is not utilized, the LE input must

be connected to an ECL Logic 1 (e.g. GND).

HFA-0003L Hysteresis Functionality

To improve performance in systems with slow transition

times, and/or high noise levels, the HFA-0003L allows the

user to easily set the amount of input hysteresis. The hyste-

resis level is set by the current flowing into the HYS input;

the larger the current the larger the level of hysteresis. This

the HYS pin and GND, and it is recommended that the input

current not exceed 1mA. The input current can be approxi-

mated from the following formula:

The table below gives approximate levels of hysteresis for

If the hysteresis function isn’t used, the HYS input may be

left floating, or may be connected to V-. The HYS input

MUST NEVER BE CONNECTED directly to GND or V+, as

device damage will occur. Before inserting an HFA-0003L

into a competitor socket, the user must ensure that the cor-

responding socket pin is a true no connect (i.e. is floating).

0.2

0.4

0.6

0.8

1.0

HYS (mV)

1

4

8

13

22

I

H

GND

V-

() 0.7V

–

–

R

H

-------------------------------------------------

=

Timing Diagram

Q

tPD

50%

LE

tS

COMPARE

LATCHED

50%

IN

tH

Q

50%

tPW